Innovation needs motivation, and there is nothing like a competitor who tries to build you daily for real conditions. From the financial point of view, vendors of RISC / Unix and AMD slump vendors have been very good at Intel, and hegemony in central data is not bigger and revenue and profits continue to record.
The latter is a lucky cloud caused by increases in hyperscalers and cloud builders, which has given some pressure competition that will be paired with Intel by its prone to OEM and ODM players.
Although Intel seeks to upgrade the monopoly that is close to supposing the server in the data center and progressing to the network (with limited results) and storage devices (better with flash memory and now being issued and potentially creating Optane 3D XPoint memory continuously), lack The competition has been very disturbing Intel’s powerful engineering.
It’s remarkable for Intel to make boxing money
and that market servers grow faster than smaller ones can eat the market, as AMD Epyc and Marvell ThunderX2 attacks and some waving swords by IBM Power9 do not have really shame on Intel’s core business. And the two-year delay of the 10 nanometer process,
which generates Intel’s deficiencies, has no effect. But in 2019, when AMD and Marvell joined this generation of devices in the advanced process of Taiwan Semiconductor Manufacturing Corp, it will come to Intel again and will be burned.
It is the task of King Koduri, Core Core vice-president and Visual Computing, general edge solution manager and Intel chief officer, and Jim Keller, senior vice president of silicon engineering, to damage the attacks.
Koduri and Keller
are the people who are responsible for Radeon GPU and Epyc CPU CPU which is restarted by AMD. And these two, among others, the main copper in Intel, put forward the attacks and defense designs at the Architecture Day event that was held this week at the former mountain of Intel founder Robert Noyce in Los Altos.
The perfect scene looks like Intel slipping high in Silicon Valley and trying to carve out a single piece of stuff for himself in the datacenter.
ROME OR CAN NOT – OR SAFE – DAY
We will get more details on what the Artists say, our conversation with both Koduri and Keller, and what we think in response to what has been revealed, but in this early part we will only take a high level of view that both laid out to begin that day.
Everyone has been accustomed to Intel’s ten-year methodology token, known by Pat Gelsinger, who previously served as chairman of Intel’s Central Data Center and was the only heir to the chip makers but had received the CEO and became the highest executive in VMware.
By typing, Intel eliminated the chip refinement process to two parts to reduce the risk, signaling a transistor process and tock shrinkage to a change of architecture that uses the process to be 12 to 18 months later when it is completed and disassembled.
With a tick-tock way, Intel can maintain a steady stream of performance, and works well. Right to the point where the fleas become larger and the sacks increase.
Intel broke the rat by 14 nanometers, extends its life and makes tick-tick-tick-tick more performance than chip-making nodes – which is necessary because of the delay in the release of 10 nanometer manufacturing processes, the laborer, Chris Williams said.
Intel five years ago it is believed that it could go out in 2015, then 2016, then in 2017, then in late 2019, and now, at least for waiters, in early 2020 when it appears “Ice Lake” Xeons. It has stretched the stretch of 14 nanometers and rolled off at 10 nanometers and some were condemned tolls that depend on the 10 nanometer process.
The lessons have no tolls that are very dependent on the previous bug
and learn to mix and play chip-engraved elements in different process and cram them into 2D packages or arrange them into 3D packages. In fact, you simply release the beep chips where you will help and you leave all the chips in the pack – such as the memory controller and the I / O controller that has a lot of power